1. Technical Field
The present invention relates to a semiconductor device and a manufacturing method for the same.
2. Related Art
DMOS (Double diffused Metal Oxide Semiconductor) transistors have, in the case of P-channel DMOS transistors, for example, a structure in which a low concentration N-type well region that is located in the surface of a semiconductor substrate on a first direction side and a high concentration P-type source region that is located in the surface of the N-type well region on the first direction side are formed by double diffusion. These DMOS transistors can handle high power and have characteristics such as a fast switching speed.
The main carriers in a P-channel DMOS transistor are positive holes, which have low mobility compared to electrons which are the main carriers in an N-channel DMOS transistor. P-channel DMOS transistors may thus have a high on-resistance compared to N-channel DMOS transistors. By, however, using a semiconductor containing N-type impurities as the gate electrode, the channel of a P-channel DMOS transistor is formed as a buried channel, and on-resistance can be reduced. JP-A-2008-235592 (FIG. 10) discloses the use of a semiconductor containing N-type impurities as the gate electrode of a P-channel DMOS transistor.
It is conceivable to provide a P-channel DMOS transistor having such an N-type gate electrode together with a logic circuit that is used with the P-channel DMOS transistor. In this case, it is conceivable to use a P-channel MOS transistor provided with an N-type gate electrode and an N-channel MOS transistor provided with an N-type gate electrode as MOS transistors constituting the logic circuit. That is, it is conceivable for the gate electrodes of the DMOS transistor and MOS transistors to all be configured as N-type gate electrodes.
However, while the channel of a P-channel MOS transistor provided with an N-type gate electrode is formed as a buried channel and on-resistance is reduced, there is also a tendency for leakage current below the threshold voltage to occur. Thus, P-channel MOS transistors provided with N-type gate electrodes may not be preferable as MOS transistors constituting the logic circuit.